An improved structure of 3.3kV 4H-SiC VDMOSFETs with lower on-resistance and reverse transfer capacitance

An improved 4H-SiC MOSFET has been presented with fewer static and dynamic losses. The novelty of the structure lies in a combination of a heavily doped n-type epitaxial layer on the drift layer (Current Spreading Layer, CSL) and a p-type implantation introduced in the middle of the JFET area (Central Implant Region, CIR). Heavily-doped CSL could significantly reduce the specific on-resistance by lowering on-resistance of JFET region and drift layer. CIR could maintain the breakdown voltage by shielding gate oxide from drain bias and reduce the reverse transfer capacitance simultaneously. At room temperature the specific on-resistance was 6.6 mΩ·cm2, 13% lower than that of DMOSFETs without CIR. The Baliga figure of merit (BFOM) was 2.6 kV2/(mΩ·cm2), 15% higher than DMOSFETs without CIR. With CIR, the turn-on gate-drain charge is 33% less than that without CIR and the figure of merit Ronsp·Qgdsp is only 768 mΩ·nC, 40% lower. Inductive load switching measurements have shown that the switch power losses of the new structure are around 22% fewer than those without CIR. In addition the fabrication process of the structure is identical to the conventional production DMOSFETs except for the epitaxial growth of CSL.