Impact of strain on access resistance in planar and nanowire CMOS devices

We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (R
_ACC
) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on R
_acc
(-21% for 4 V V
_B
and -53% for -1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under ε
_n/p
=0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs.