Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability

This paper shows high-pressure anneal (HPA) as a performance booster for Si-passivated strained Ge (sGe) p-channel FinFET and gate-all-around (GAA) devices. Improved interface quality and hole mobility (~600 cm
²
/Vs) are obtained on FinFET after HPA at 450°C. While V
_th
is tuned by ~400 mV using TiAl work function metal (WFM), HPA-induced increases in J
_g
and NBTI are suppressed by barrier layer engineering under the TiAl. Finally, the optimized HPA is also shown to improve the electrostatics and overall performance of GAA devices, reaching SS
_lin
of 65 mV/dec at L
_g
=60 nm and a Q factor of 15 with low I
_off
of ~3×10
^-9
A/μm.