A Phase-Locked-Loop optimal parameter design by improved discrete Particle Swarm Optimization

The main design parameters of Phase-Locked-Loop (PLL) are charge pump current, loop filter resistor, loop filter capacitor, voltage controlled oscillator (VCO) output slope and the divisor of divider. The above-listed parameters are directly relative to PLL performance. In a conventional PLL design, designers implement circuits to satisfy the specification on chip by simulator. However, it usually has to modify the expected specification due to process voltage temperature (PVT) variation when implementing. In this paper, we proposed a design to search optimal PLL parameters by improved discrete Particle Swarm Optimization (PSO) and applied digital control to modulate PLL to optimal performance.