Novel TFET circuits for high-performance energy-efficient heterogeneous MOSFET/TFET logic

TFET's steep subthreshold slope and asymmetric I
DS
-V
DS
characteristics enable energy-efficiency and novel circuits that are not possible with MOSFETs. Logic with low-V
DD
and memory with low-V
MIN
are required and possible with TFET. To increase performance despite low-V
DD
, circuits and logic are re-designed for TFET's unique I–V characteristics. Asymmetric I
DS
-V
DS
improves circuit design. Efficiency gains from transistor steep-slope enable heterogeneous MOSFET-TFET logic re-design for higher clock rate and greater parallelization.