1×- to 2×-nm MTJ switching at sub-3 ns pulses with compatible current in sub-20 nm CMOS for high performance embedded STT-MRAM

Magnetization switching was confirmed for sub-3-ns pulses below 100 μA in pMTJs down to 16 nm in diameter. The MR ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of -6 (10
^-6
) were demonstrated. Read and write current margins, which were important device designs, were sufficiently large to avoid read disturbances. Moreover, 1×- to 2×-nm MTJs had sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remained stable after 10
¹²
write events. We believe these p-MTJs are potentially available for cache memory in sub-20-nm CMOS and reduce power consumption and while increasing cache capacity.