Evaluation of ultra-low power Tunneling Field Effect Transistor power management unit

In this paper, we propose a TFET (Tunneling Field Effect Transistor) PMU (power management unit) of R80515 for ultra-low power. Both the dynamic power and leakage power are evaluated by HSPICE circuit simulation with Verilog-A models. From the simulation, we find the dynamic power of TFET circuits can be reduced by 80% and leakage power reduction can be nearly 30% compared with 130nm CMOS (Complementary Metal Oxide Semiconductor) implementation. The results indicate that TFET can achieve much higher power efficiency and the replacement can be vital to the whole design.