Design of a spike detector for fully Integrated Neuromodulation SoC

The paper presents a new spike detector proposed for the Neuromodulation SoC. The SoC designed combines the 64 acquisition channels with digital compression and simulation. The objective of this work is to design a spike detector for event detector. In literature several designs available which uses above 90nm technology with supply voltage greater than 1.8V. The spike detector consists of an non linear energy operator, moving average filter, pipeline stage, processing elements like multiplier, adder and comparator. The design supports adaptive thersholding for event detector which depends on the physiological parameters like electrode movements, skin impedance, etc. This work proposes a design in 65nm and 45nm, the system works in supply voltage less than 1V by which the power consumption is reduced. The lower technology allows the design to be area efficient.