Reliability-driven high-level synthesis with clock frequency considered

The clock frequency selection has a great impact on the highlevel synthesis result (including both the operation scheduling result and the functional unit binding result). Since different high-level synthesis results lead to different circuit reliabilities, the clock frequency selection greatly influence the circuit reliability. Based on this observation, in this paper, we study the high-level synthesis with clock frequency considered. Our objective is to maximize the circuit reliability under the latency constraint and the area constraint. We propose a polynomial time heuristic algorithm to deal with this problem effectively and efficiently. Experimental results show that, in each benchmark circuit, compared with the previous work, our approach can improve the circuit reliability under the same design constraints.