ATPG method with a hybrid compaction technique for combinational digital systems

In this paper, the Test Pattern Generation (TPG) with a new simple hybrid (dynamic and static) compaction technique for combinational logic circuits and systems is presented. Digital systems are implemented nowadays on an advance VLSI technology, which is called Field Programmable Gate Array (FPGA). The test procedure requires a deliberate introduction of faults in the System Under Test (SUT). FPGA circuits and systems are developed and written in Hardware Description Languages (HDLs). In addition, a novel method is also proposed and implemented in order to intentionally inject faults in the Verilog HDL code design of the SUT. It covers all possible fault locations in the SUT. This approach provides high quality compact test vectors and efficient memory utilization in comparison with other state-of-the-art methods. Not only are the hardness of individual faults and the sensitiveness of fault locations determined, but also their effectiveness is proposed in the fault tolerance strategy.