A dynamic reprogramming scheme to enhance the reliability of RRAM

In this paper, an algorithm level circuit design scheme is developed based on the typical types of error of Resistive Random Access Memory (RRAM). Error Correction Circuit (ECC) is added to the original peripheral read and write circuit of RRAM to increase error-tolerance rate of the circuit and a dynamic reprogramming mechanism with low power consumption is further added. This scheme could raise the read and write accuracy of RRAM and reduce the probability of read errors incurred by retention failure to enhance the reliability of RRAM. In addition, this scheme adds buffer in the circuit in accordance with the read characteristic of RRAM so that the write scheme of RRAM could be applied in the system level perfectly.