Analysis of Linear-Doped Si/SiC Power LDMOSFETs Based on Device Simulation

This paper presents the design and optimization of a 600 V silicon-on-silicon carbide (Si/SiC) laterally diffused MOSFET with linear doping profile in the drift region for high-temperature applications. The proposed structure has an embedded silicon-on-insulator (SOI) layout through which the traditional graded doping theory for SOI can be applied in the Si/SiC architecture. An SOI counterpart is introduced as a benchmark and modeled alongside the proposed structure. Comparisons between them show that they have the near-identical OFF-state and breakdown characteristics, with a significant tunneling leakage component emerging above 450 V. In the ON state, the Si/SiC device has higher electrical resistance but much lower thermal resistance, leading to less self-heating and higher reliability.