Influence of the Ge amount at source on transistor efficiency of vertical gate all around TFET for different conduction regimes

In this work, the influence of the Ge amount at source on transistor efficiency and intrinsic voltage gain of vertical gate all around TFET is experimentally evaluated, comparing three different source compositions. The reference transistor has a source of 100% of Si, and the studied devices have 27% and 100% of Ge at the source. The increase of the Ge amount at source enhances the tunneling current, without degrading the off state current, improving the subthreshold region characteristics and reducing the onset voltage. At the same current level, devices with higher percentage of Ge present a higher Early voltage and improved efficiency, resulting in an increase of the intrinsic voltage gain. Comparing at the same gate bias, Ge source devices are also better due to their higher drain current value. At weak conduction regime, all devices show better analog characteristics due to their higher efficiency values. Considering the better performance of Ge source devices, two different HfO
₂
thicknesses were also analyzed (3 nm and 2 nm). The device with thinner HfO
₂
layer presents better transistor efficiency at both conduction regimes due to its better electrostatic coupling. However, when using high values of gate voltage, this device has a strong degradation on the intrinsic voltage gain.