Scalable analytic placement for FPGA on GPGPU

The growth in field-programmable gate array (FPGA) capacity has outpaced improvements in serial processor speeds for the last decade and will continue for the foreseeable future. Unfortunately, as modern FPGAs have millions of logic elements and continue to grow, the compilation of designs can take hours or even days to complete. As a result, the runtimes of placement and routing flow have become a major concern for FPGA users and vendors alike. Roughly half the total compilation time is spent in the placement phase. Analytic placement algorithms solve the FPGA placement problem quickly. With an aim toward developing a scalable FPGA placement algorithm, we present a parallel analytic placement algorithm implemented on general-purpose computing graphics processing units (GPGPUs). The proposed analytic placer is scalable, that is, the placer maintains parallel efficiency as the problem size grows and number of parallel workers increase. Our algorithm is a parallelized version of the serial analytic placement algorithm StarPlace and achieves speedups of 13-31 times compared to this serial version. The proposed parallel algorithm is on average 78 times faster than the academic tool versatile place and route (VPR) when run in its fast, wirelength driven mode. The wirelength is on average 3% lower than VPR, with a 24% reduction in critical-path delay.