Si interposer with 10×100μm copper TSVs for 2.5D integration

2.5D integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. Through silicon via (TSV) is one of the key elements for 2.5D integration. This paper presents a full process integration solution for interposer with 10×100μm copper filled TSVs, which involves TSV etch, TSV insulation, barrier and seed layer deposition, TSV filling, TSV reveal, etc. Void-free TSV filling and robust TSV backside pickup structure are achieved. Electrical performance of TSV insulation is also studied in order to give reliability guidelines for process optimization. It is also found that the step coverage of PECVD TEOS film is less than 15% and the leakage current is less than 10-11 A/cm2 (at 1MV/cm). Thermal oxide provides excellent step coverage (>90%) and lower leakage current. Finally, multi-die 2.5D interposer with high density Cu TSVs is achieved.