Backside films and charging during via etch in LOCOS and STI technologies

Films on the back of wafers affect charging during via etch for two CMOS technologies. One technology is LOCOS-based (local oxidation of silicon), with the backside conductive during critical process steps. The other is STI-based (shallow trench isolation), with the backside insulated during key steps. The conductive backside causes charging damage during via etch, as evidenced by threshold voltage shifts and the increased hot-electron sensitivity of monitoring devices. Data from large and small vias indicate that the electron-shading mechanism of charging damage is responsible for the effect.