High speed static frequency divider design with 111.6 GHz self-oscillation frequency (SOF) in 0.13 µm SiGe BiCMOS technology

A speed optimization scheme for static frequency dividers based on master-slave flip-flops is presented. As a proof of the concept, the design of a divide by two static frequency divider in 0.13 μm SiGe BiCMOS technology (with f
_t
gt; 300 GHz and f
_max
gt; 450 GHz) is reported. The circuit exhibits the highest self-oscillation frequency (SOF) of 111.6 GHz among the existing SiGe technology based static frequency dividers. With singleended sine wave clock input, divider is operational from 6 to 128.7 GHz (limited by measurement equipment). At dual power supply with V
_cc
= 3 V and V
_ee
= -1.9 V, the circuit consumes 40 mA per latch.