Segmented plated-thru-hole design in flip-chip packaging for improved electrical performance

This paper describes a novel segmented plated-thra-hole (PTH) structure in flip-chip packaging design to address the current and future high-speed signaling and power integrity problems. The design is capable to resolve the high-frequency coupling from signal integrity perspective, as well as power integrity's loop inductance and resistance issues, which are commonly associated with today's ultra-small form-factor substrate design. In the signal integrity study, the innovative segmented PTH design was applied to next-generation USB 3.1, also known as SuperSpeed+ USB which is operating at 10Gbps. It is ascertained that a 4-layer packaging solution for enabling USB 3.1 is feasible with the novel design, of which a conventional 4-layer packaging design could not offer. Power integrity assessment, on the other hand, shows performance boost could be achieved through segmented PTH design, even with only half of the PTH count compared to the conventional substrate design, thus indicating viable smaller package design or package-level capacitors reduction.