Release holes: Physical implementation checks for thin films packaging

The question of MEMS packaging with hermetic protection has led to the development of thin-film packaging solutions. Indeed, 200mm thin-film packaging is low-cost, ultra-compact, fully CMOS compatible and can be used for all kinds of MEMS devices. The core of this process is a cavity created by a sacrificial layer that is covered with a mineral cap and an organic layer to seal it. One of the main challenges is to adjust the size and location of the holes required to fully release the sacrificial layer while allowing an easy occlusion of the holes afterwards. Consequently, the holes network pattern has to be well designed before manufacturing. Therefore a new methodology is presented to guarantee higher process yield and robustness. During the layout phase, using a standard Design Rules Check environment, an etching simulation can be used to show the remaining sacrificial layer and help in adjusting the size and location of the holes if necessary. Easy to integrate in a standard design environment, this innovative solution leads to substantial benefits in the manufacturing of any thin film packaged MEMS. In this paper, this approach is assessed through an actual packaged device.