Tunable CMOS delay gate with reduced impact of fabrication mismatch on timing parameters

This paper presents the analysis and design of a simple one-stage tunable delay gate with improved matching properties as compared with the commonly used “current starved inverter”. The operation of two delay lines employing these structures in a standard 90 nm CMOS technology was verified based on the post layout mismatch Monte Carlo simulations. Accounting for the fabrication mismatch, the delay generated by the proposed “output-split inverter” (OSI) circuit is about 10-30% more accurate as compared to the conventional current starved inverter occupying the same chip area.