Low voltage DCI based low power VLSI circuit implementation on FPGA

In this paper, we study the effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption. In this work, we achieved 50% dynamic power reduction at 1.5V output driver voltage, 35.2% dynamic power reduction at 1.8V output driver voltage in comparison to 2.5V output driver voltage in DCI based IO standard implementation on input or output port in target design. Target device XC6VLX75TFF484-1 is a Virtex-6 FPGA of -1 speed grade and 484 pins is used for implementation of this design. Target Design is RAM-UART memory interface. XPower 13.4 is used for power analysis of our low power memory interface design. ISim is simulator to generate waveform. Planahead is used for design, synthesis and implementation.