Hierarchical optimization of TSV placement with inter-tier liquid cooling in 3D-IC MPSoCs

Thermal management in 3D-ICs is a significant constraint, owing to the high heat flux (~200 W/cm
²
) and the vertical integration density. The vertical inter-layer connections are achieved using the through silicon vias (TSV). The placement and density of these TSVs are restricted by the pitch size, hotspots and fabrication costs. Moreover, the placement of TSVs effects the thermal gradients and the overall interconnect length. In this paper, an optimized architectural framework for the TSV placement with inter-tier liquid cooling is proposed. In particular, the framework introduces a weight-based simulated annealing (WSA) algorithm and incorporates power density in the cost function estimate for a balanced thermal gradient distribution. In addition, we propose a wholistic interconnect length estimate to optimize the TSV placement. The WSA algorithm implemented on MCNC'91 and GSRC benchmarks demonstrates up to 16% reduction in the average area of the chip. Furthermore, TSV rearrangement reduced the overall interconnect length 4%-33% across the MCNC'91 benchmarks.