A 90-μW 16 bit 20 KHz-BW feedforward double-sampled sigma-delta modulator in 0.18 CMOS

This paper presents a low power, area-efficient feedforward double-sampling sigma delta modulator. A novel double sampled structure that combines two techniques was proposed. The DAC capacitor reset technique is used to eliminate the noise folding caused by the mis match between two sampling branches; a direct summation scheme obviates analog adder in the front of the quantizer, which greatly relaxes the timing constraints in the feedforward path. The modulator is implemented in the SMIC 0.18um technology; the simulation results show the modulator provides 102.5dB SNDR over a 20-KHz signal bandwidth. The power consumption of modulator is 90μW under 1.5V power supply.