Dual-injection sub-harmonic injection-locked frequency tripler

This paper presents a sub-harmonic injection-locked frequency tripler. This injection-locked frequency tripler was implemented with TSMC 0.18 μm 1P6M CMOS process. The feature of the proposed circuit employs the way of the dual-injection to lock the triple-frequency signal with higher output power. The available output power after the buffer stage of 0.6 dB gain is -2.88 dBm. The power consumption of the core circuit takes 9.22 mW from a 1.8 V power supply. The measured locking range is from 21.38 GHz to 23.37 GHz.