The execution pipeline of the Intel i486 CPU

The integer instruction execution pipeline of the Intel i486 processor is described. The performance of the i486 CPU in a system is related to several systems based on competitive reduced-instruction-set-computer (RISC) processors. The instruction pipeline was designed to execute instructions at a sustained rate of 1 clock per instruction. A key to achieving this rate was the integration of the cache into the pipeline. Another key was pipelining the instruction decoder into two stages to provide a sustained throughput of 1 instruction per clock, while decoding the complex instruction formats of the Intel 386 family architecture. An overview of the pipeline is provided by giving a brief description of each pipeline stage. Then several multiple instruction examples are given to illustrate some key properties of the pipeline.<
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