A current reference pre-charged zero-crossing pipeline-SAR ADC in 65nm CMOS

Using a current reference pre-charge technique, the need for power hungry low impedance voltage reference buffers is eliminated in a zero-crossing pipeline-SAR ADC. The 40MS/s ADC prototype, implemented in a 65nm CMOS process, achieves an SFDR/SDR/SNDR of 70dB/66dB/59.5dB at Nyquist, while occupying 0.95mm² and consuming 4.5mW from a 1.35V supply, requiring no additional power for reference buffers.