Decimation filter with novel MVTL XOR gate

A single-rail Modified Variable Threshold Logic (MVTL) decimation filter is designed by employing a novel XOR gate, which overcomes the difficulty of the lack of a good inverter in the MVTL logic family. A 10-bit deep-pipelined decimation filter consisting of about 700 junctions in a 5 mm/spl times/5 mm chip with power consumption of 0.4 mW is designed.