Hardware compression solution based on HWT for low power image transmission in WSN

Software implementation costs of most algorithms, designed for image compression in Wireless Sensor Networks, doesn't justify their use to reduce the energy consumption and delay transmission of images. Even thought the hardware solution look to be very attractive for this problem, a specific careful should be paid when designing a low power algorithm for image compression and transmission over these systems. The aim of this paper is to present and evaluate a hardware implementation for user-driven image compression scheme designed to meet the energy constraints of image communication over Wireless Sensors Networks (WSNs). The proposed encoder will be considered as a co-processor for tasks related with image compression and data packetization. In this paper, we discuss both of the hardware architecture and the features of this encoder circuit when prototyped on FPGA and ASIC solutions.