A 2.0 to 3.0 GHz CMOS low noise amplifier and its applications

This paper presents a 2 GHz to 3 GHz Low Noise Amplifier (LNA) design based on a cascode topology. The proposed method is addressed to optimize noise performance and power efficiency while maintaining good input and output matching. This LNA has a measured power gain of 13.5dB and noise figure of 1.5 dB. The output insertion loss S
₂₂
is -9dB. input return loss (s11) is -22dB. The design simulation process is using Advance Design System (ADS) software and implemented in TSMC 0.18 μm CMOS technology with very low power dissipation.