3-D integration requirements for hybrid nanoscale-CMOS fabrics

Several nanoscale-computing fabrics based on novel materials such as semiconductor nanowires, carbon nanotubes, graphene, etc. have been proposed in recent years. However, their integration and interfacing with external CMOS has received only limited attention. In this paper we explore integration challenges for nanoscale fabrics focusing on registration and overlay requirements especially. We address the following questions: (i) How can we mitigate the overlay requirements between nano-manufacturing and conventional lithography steps? (ii) How much overlay precision is necessary between process steps? and (iii) What is the impact on yield if different overlays are used? We propose and evaluate a new 3D integration approach that combines standard CMOS design rules with nano-manufacturing constraints. For a nanoprocessor design implemented in N
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ASIC (a hybrid nanowire-CMOS fabric) we show that a 100% yield is achievable even for overlay precisions achievable with current CMOS manufacturing (3σ=±8nm, ITRS 2009) while still retaining 3X density advantage compared to a projected 16nm CMOS scaled design.