Drain current variability and MOSFET parameters correlations in planar FDSOI technology

We present for the first time an extensive experimental study of the statistical variability of the drain current (I
_D
) in 6nm thin undoped Silicon-On-Insulator (SOI) MOSFETs. I
_D
variations (σ
_ID
) are found to be highly correlated with both threshold voltage (V
_T
) and ON-state resistance (R
_ON
) fluctuations. Their respective contributions cannot be directly added to capture σ
_ID
because of an advantageous ΔV
_T
/ΔR
_ON
correlation. Taking into account such correlations is of great interest for an accurate definition of spice model corners. We also evidence the main technological sources of I
_D
fluctuation. Improving the access resistances (R
_SD
) enables to lowering the R
_ON
variability. Engineering of the source/drain implantations (Low temperature C+P co-implant) mainly reduces the current (I
_SAT
, I
_OFF
) variability through an improved V
_T
control.