FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric

In today's microprocessors, the cache architecture is highly optimized for one particular design and cannot be changed after fabrication. While allowing efficient implementations in dedicated logic, this inflexibility also implies that new techniques cannot be deployed in the field. This paper presents Flex Cache, a flexible cache architecture that uses on-chip reconfigurable fabric to enable new extensions to be added in the field after fabrication. We evaluate the flexibility and efficiency of the architecture through an RTL prototype implementation of the cache along with example extensions such as cache performance counters, side-channel protection, prefetching, various replacement policies and computation acceleration. The results show that various types of extensions can be realized on Flex Cache with minimal impact on performance, power, and area.

I. Introduction

The memory hierarchy plays a central role in modern microprocessors. Researchers have proposed numerous ideas and techniques that augment caches to improve performance, enhance security and reliability, and extend functionality [1], [2], [3]. However, today's cache implementation is typically fixed and optimized for a particular cache design. This enables the cache implementation to be highly efficient, yet at the same time means that even a small change in the cache requires re-design and re-fabrication of a microprocessor. Such a hardware change is often prohibitively expensive because of ever increasing NRE (Non-Recurring Engineering) costs.