Buck and boost converter design optimization parameters in modern VLSI technology

This paper presents the feasibility challenges of designing dc-dc buck and boost converter in nano-scale. With the gradual development of VLSI design platforms, new issues have been introduced and presented to the power electronics circuit experts and VLSI engineers. Today's VLSI industry has reached the technology well within the nano-meter range. The consequence of implementing the basic power electronics converter topology such as buck and boost converter into this technology is discussed in this paper. It also covers the optimization issues between conduction modes, switching frequencies, efficiency and chip area. Fabrication issues are discussed, with the limitations of use of elements such as inductor, capacitors and resistors. Tradeoffs between chip area and performance are highlighted. Design challenge for optimum switching frequency, off the chip capacitor, and strategies to minimize switching and conduction losses are also discussed.