An 8×10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects

A serial I/O chip set in 45 nm SOI CMOS is mounted via 50 μm pitch micro-C4 bumps to a silicon carrier and communicates over ultra-dense interconnects with pitches of between 8 μm and 22 μm. With DFE-IIR RX equalization, data is received over distances up to 6 cm with channel losses as high as 16.3dB. The energy efficiency is better than 6.1pJ/bit.