Taming Compiler to Work with Multicore Processors

We present a parallelization scheme involving extracting intra block parallelism within sequential programs which are in SSA form and scheduling block on to multicore processor. Since we are working on SSA form program, we are able to exploit more parallelism compared to existing parallelization compilers. Also an attempt is made to schedule to multiple cores taking by number of registers into consideration. At the end we show how our approach will give solution to direct cache coherence problem.