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Variability aware modeling for yield enhancement of SRAM and logic | IEEE Conference Publication | IEEE Xplore

Variability aware modeling for yield enhancement of SRAM and logic


Abstract:

Anticipating silicon response in the presence or process variability is essential to avoid costly silicon re-spins. EDA industry is trying to provide the right set of too...Show More

Abstract:

Anticipating silicon response in the presence or process variability is essential to avoid costly silicon re-spins. EDA industry is trying to provide the right set of tools to designers for statistical characterization of SRAM and logic. Yet design teams (also in foundries) are still using classical corner based characterization approaches. On the one hand the EDA industry fails to meet the demands on the appropriate functionality of the tools. On the other hand, design teams are not yet fully aware of the trade-offs involved when designing under extreme process variability. This paper summarizes the challenges for statistical characterization of SRAM and logic. It describes the key features of a set of prototype tools addressing that required functionality together with their application to a number of case studies aiming at enhancing yield at product level.
Date of Conference: 14-18 March 2011
Date Added to IEEE Xplore: 05 May 2011
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Conference Location: Grenoble, France

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