Variability aware modeling for yield enhancement of SRAM and logic

Anticipating silicon response in the presence or process variability is essential to avoid costly silicon re-spins. EDA industry is trying to provide the right set of tools to designers for statistical characterization of SRAM and logic. Yet design teams (also in foundries) are still using classical corner based characterization approaches. On the one hand the EDA industry fails to meet the demands on the appropriate functionality of the tools. On the other hand, design teams are not yet fully aware of the trade-offs involved when designing under extreme process variability. This paper summarizes the challenges for statistical characterization of SRAM and logic. It describes the key features of a set of prototype tools addressing that required functionality together with their application to a number of case studies aiming at enhancing yield at product level.

I. Introduction

Advances in CMOS VLSI circuit design has primarily relied on technology improvements derived from technology scaling. However, process variability and especially its intra-die uncorrelated portion has significantly increased the uncertainty in the response of sub-45nm CMOS circuits. Today, intra-die (also known as local random) process variations are main contributors to statistical circuit responses (e.g., delay and power). Such increase of process variability at every technology node has imposed new challenges to the design and characterization of SRAM and logic cells.