Proactive recovery for BTI in high-k SRAM cells

Recent studies of BTI behavior in SRAM cells showed that for high-K metal gate stack technology, PBTI induced V
_th
shift in NMOS is as significant as NBTI induced V
_th
shift in PMOS. Previous techniques of mitigating NBTI in SRAM focus mainly on PMOS and thus lack the ability to mitigate PBTI of NMOS transistors. In this paper, we propose a novel design to recover 4 internal gates within a SRAM cell simultaneously to mitigate both NBTI and PBTI effects. In the evaluated L2 cache, our technique effectively slows down the cell failure probability increase, and achieves 4.64/2.86× (best/worst case) lifetime improvement over normal design.