Robustness analysis of 6T SRAMs in memory retention mode under PVT variations

Process variability is becoming a major challenge in CMOS design of general and embedded SRAMs in particular due to continuous device scaling. The main problems are the increased static power and reduced operating margins, robustness and reliability. A common way to reduce the static power consumption of an SRAM memory array is to decrease its supply voltage when in memory retention mode. However, this leads to a further reduction in memory robustness. The most common tool for statistical analysis of circuits under process variability is standard Monte Carlo simulation which has been proven to be too expensive when applied on an ultra dense SRAM. In this paper a statistical robustness analysis method is proposed based on decoupling statistical integration from robustness region determination in the parameter domain. The robustness is estimated with a ~ 556X speed up relation to Monte Carlo and an error of ~ 1%.