Robust 6T Si tunneling transistor SRAM design

SRAMs based on tunneling field effect transistors (TFETs) consume very low static power, but the unidirectional conduction inherent to TFETs calls for special care when designing the SRAM cell. In this work, we make the following contributions, (i) We perform the first study of 6T TFET SRAMs based on both n-type and p-type access transistors and determine that only inward p-type TFETs are suitable as access transistors. However, even using inward p-type access transistors, the 6T TFET SRAM achieves only the write or the read operation reliably, (ii) In order to improve the reliability of 6T TFET SRAMs, we perform the first study of four leading write-assist (WA) and four leading read-assist (RA) techniques in TFET SRAMs. We conclude that the 6T TFET SRAM with GND lowering RA is the most reliable 6T TFET SRAM during write and read, and we verify that it is also robust under process variations. It also achieves the best performance and reliability, as well as the least static power and area, in comparison to other existing TFET SRAM structures. Further, it not only has comparable performance and reliability to the 32nm 6T CMOS SRAM, but also consumes 6-7 orders of magnitude lower static power, making it attractive for low-power high-density SRAM applications.