A High Speed VLSI Architecture of SPIHT without Lists for Real-Time Applications

In this paper, we present a bit-plane parallel architecture for a modified SPIHT without lists algorithm using the breadth first search for coefficient trees. This scheme can ensure that the quality of reconstructed images is almost the same with that of SPIHT with lists. Compared with the other architectures, our architecture has advantages of high parallelism, no intermediate buffer and ability to error resilience as the coefficient trees are visited independently.