An efficient FPGA-based hardware implementation of MIMO wireless systems

Emerging multiple-input multiple-output (MIMO) systems are regarded to play a key role in 4G wireless systems in order to achieve higher data rate while maximizing spectral efficiency. This paper presents a proficient hardware realization of MIMO systems that is designed and implemented on a Xilinx Virtex™-4 XC4VLX60 Field Programmable Gate Arrays (FPGA) device. The MIMO encoder implementation is straight forward; however, the decoder implementation is little more complex as it requires resource utilization. The hardware, presented in this paper, utilizes the resources by adopting the technique of parallelism. A comprehensive explanation of the complete design process is provided, including a highlight on the tools used in its development. The results are obtained for 2 × 2 MIMO system for encoding and decoding at the transmitter and the receiver. The system is developed based on modular design which simplifies system design, eases hardware update and facilitates testing the various modules in an independent manner.