A simple mathematical model for clocked QCA cells

In this paper Equivalent circuit of a three input majority gate for clocked implementation state is presented. The output voltage of a clocked logical QCA (quantum-dot cellular automata) circuit which is a three-input majority gate is simulated. For this scope a model simulated with MATLAB is used to simulate clocked QCA circuits. By using this model, it is possible to design and simulate clocked combinational QCA and hybrid circuits including QCA and other nano devices. Combined theoretical and experimental studies, show that the QCA-based circuits potentially lead to circuits with densities that are 3–4 orders of magnitude beyond what CMOS (Complementary metal-oxide-semiconductor) circuits can provide. It should dissipate very little power, and could be clocked at an extremely high frequency (adiabatically at 1 THz). Clocking in QCA provides power gain, reduces power dissipation, and provides a means for memory features in the cells and QCA latches. By introducing clocked control of the QCA cell, computational pipelining can be achieved.