Master-Slave ternary D flip-flap-flops with triggered edges control

The paper is dedicated to Master-Slave ternary D flip-flap-flops with triggered edges control. First, the flip-flap-flops with binary clock are implemented. Next, the C0, C1 and C2 ternary gates are used to improve the control of triggered edges for flip-flap-flops with ternary clock. The 3-trits shift register realized with both types of flip-flap-flops (with binary and ternary clocks) is also presented. The correct operation of the flip-flap-flops was demonstrated by simulations in the Simulink environment.