Devices and Input Vectors are Shaping von Neumann Multiplexing

This paper starts by reviewing many of the gate-level reliability analyses of von Neumann multiplexing (vN-MUX). It goes on to detail very accurate device-level (CMOS technology specific) analyses of vN-MUX with respect to threshold voltage variations, taking into account both the gates' topology as well as the input vectors. Such results are essential for a clear understanding of vN-MUX when considering the unreliable behavior of future nanodevices. These analyses should change the “view from the top” as revealing a different picture from the well-known gate-level theoretical and simulation results. The findings presented here are also able to explain certain apparently abnormal behaviors of vN-MUX reported based on Monte Carlo simulations, and should have implications for the appraisal and the design of future fault-tolerant nanoarchitectures.