Optimizing correctly-rounded reciprocal square roots for embedded VLIW cores

This paper presents an optimized software implementation of the reciprocal square root function x ¿ x
^-1/2
, for IEEE binary32 floating-point data and with correct rounding to nearest. The main feature of this implementation is high instruction-level parallelism (ILP) exposure, which results here from an extension of the bivariate polynomial evaluation-based method of as well as from the design of a specific rounding procedure. This implementation proves to be very efficient for some VLIW processor cores like STMicroelectronics' ST231 (used mainly for embedded media processing), for which a low latency of 29 cycles has been measured.