A general mathematical model of probabilistic ripple-carry adders

Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible to trade correctness of circuit operations for potentially significant energy saving. For systematic design of probabilistic circuits, accurate mathematical models are indispensable. To this end, we propose a model of probabilistic ripple-carry adders. Compared to existing models, ours is applicable under a wide range of noise assumptions, including the popular additive-noise assumption. Our model provides recursive equations that can accurately capture propagation of carry errors. The proposed model is validated by HSPICE simulation, and we find that the model is able to predict multi-bit error-rates of a simulated probabilistic ripple-carry adder with reasonable accuracy.