EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications

In this paper, a new framework EmCodeSyn is introduced for visual debugging, execution and code synthesis from multi-rate data flow based specifications. EmCodeSyn is an attempt to create a formal semantics based visual framework for specifying safety critical applications such as automotive control, avionics fly-by-wire control, etc. In contrast with SIMULINK/Stateflow, LabVIEW and other visual tools, EmCodeSyn is based on a synchronous programming paradigm akin to the polychronous language SIGNAL. The formalism on which this work is based, is called MRICDF (multi-rate instantaneous channel connected data flow). The specification formalism has relational semantics, which enables static rate-analysis for scheduling the computation in the code generation stage. Hierarchical data flow specification with minimal amount of control specification makes it easier for designers to compose existing MRICDF models to create larger ones. Once the feasibilty of an MRICDF design is verified, code synthesis is performed by the tool to generate C code. EmCodeSyn design methodology provides a visual framework for generating verifiable deterministic code from synchronous specification based on MRICDF formalism.