New look-up-table optimizations for memory-based multiplication

Two new techniques are presented in this paper, for the reduction of look-up-table (LUT) size of memory-based multipliers to be used in digital signal processing applications. It is shown that by simple sign-bit exclusion, the LUT size is reduced by half at the cost of a marginal area overhead. Moreover, a novel anti-symmetric product coding (APC) scheme is proposed to reduce the LUT size by further half, where the LUT output is added with or subtracted from a fixed value. It is shown that the optimized LUTs for small input width could be used for efficient implementation of high-precision LUT-multipliers, where the total contribution of all such fixed offsets could be added to the final result or could be initialized for successive accumulations. The proposed LUT-multiplier and the existing ones are coded in VHDL and synthesized by Synopsys Design Compiler using TSMC 90 nanometer library. The proposed optimized LUT-multiplier is found to involve less area and less multiplication time than the existing LUT-multipliers. The conventional LUT-multiplier and the odd-multiple storage LUT of [1] involve nearly 56.8% and 26.2% more area-delay product, in average, for 16-bit input than the proposed LUT design.