Detecting errors in digital communications with CRC codes implemented with FPGA

Generally speaking, cyclic redundancy checks (CRCs) are used to detect errors from noise in digital data transmission. The technique is also sometimes applied to data storage devices, such as a disk drive. They also have been turned to verify the integrity of files in a system in order to prevent tampering and suggested as a possible algorithm for manipulation detection codes. It has been known that a CRC will not detect all errors but with random noise it is unlikely. In this paper, we present an efficient algorithm for parallel computation of the CRC in data transmission.