A single chip videophone video encoder/decoder

This paper describes the realization of a single chip CODEC for a video telephone terminal. Several image compression architectures have already been reported. This chip allows implementation of the video sub-system of a consumer video telephone with only 4 chips including this CODEC, a dedicated display controller chip, a standard low-end ST9 microprocessor, and a standard video RAM component. The chip encodes and decodes simultaneously 15 QCIF (144/spl times/176 pixels) images per second, according to the H.261 norm. It is optimized for bit streams in the 48 kb/s to 128 kb/s range, but lower bit rates can be accommodated. The chip also encodes or decodes still CIF (288/spl times/352) images. A flow diagram of the embedded algorithm is presented.